1. Field of the Invention
The present invention relates to a calibration method, an A/D converter, and a radio device.
2. Description of the Related Art
In a parallel analog/digital (A/D) converter as typified by a flash A/D converter, comparators are arranged in parallel with one another in accordance with a required resolution. A plurality of pre amplifiers in series are disposed at an input port side of each of the comparators. Each comparator compares a voltage of a pre-amplified analog signal with a reference voltage to find which one of voltages is higher than the other. The A/D converter outputs a digital signal according to the comparison result. In the A/D converter, the resolution is degraded because of the presence of offset voltages of the comparators and the pre amplifiers.
One technique to reduce the degradation is disclosed in “A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:EXPRESS BRIEFS, JULY 2008, VOL. 55, NO. 7, p. 668-672. In this reference, the A/D converter performs calibration of an offset of the pre amplifier located at a first stage in series.
However, in the conventional method, the offset voltage of the pre amplifier at the first stage is amplified by a pre amplifier at a second stage in series. Accordingly, a voltage range to calibrate the offset voltage needs to be set large. This makes it difficult to design an operation with a low power supply voltage. Further, if the offset voltage of the pre amplifiers at the first stage is calibrated as in the conventional method, a residual offset of an interpolation voltage cannot be calibrated in a parallel A/D converter when using an interpolation technique.